R10000 Microprocessor User's Manual
5. Secondary Cache Interface
The processor supports a mandatory secondary cache by providing an internal secondary cache controller with a dedicated secondary cache port.
The cache's tag and data arrays each consist of an external bank of industry-standard synchronous SRAM (SSRAM). This SSRAM must have registered inputs and outputs, asynchronous output enables, and use the late write protocol (data is expected one cycle after the address).
Chapter Contents
- 5.1 - Tag and Data Arrays
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- 5.2 - Secondary Cache Interface Frequencies
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- 5.3 - Secondary Cache Indexing
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- 5.4 - Secondary Cache Way Prediction Table
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- 5.5 - Secondary Cache Tag
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- 5.6 - Read Sequences
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- 5.7 - Write Sequences
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Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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